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january 2009 rev 13 1/37 1 m24512-x m24256-bx 512 kbit and 256 kbit serial i2c bus eeprom with three chip enable lines features supports the i 2 c bus 100 khz standard-mode, 400 khz fast-mode and 1 mhz fast-mode plus supply voltage ranges: ? 1.7 v to 5.5 v (m24256-bf) ? 1.8 v to 5.5 v (m24xxx-r) ? 2.5 v to 5.5 v (m24xxx-w) write control input byte and page write random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection more than 1 000 000 write cycles more than 40-year data retention packages ?ecopack ? (rohs compliant) table 1. device summary reference part numbers m24512-x m24512-r, M24512-HR, m24512-w m24256-bx m24256-bf, m24256-br, m24256-bhr, m24256-bw so8 (mw) 208 mils width tssop8 (dw) so8 (mn) 150 mils width wlcsp (cs) www.st.com
contents m24512-x, m24256-bx 2/37 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 16 3.10 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 17 3.11 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.14 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.15 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m24512-x, m24256-bx contents 3/37 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables m24512-x, m24256-bx 4/37 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. operating conditions (m24xxx-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 9. operating conditions (m24xxx-r and m24xxx-hr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. operating conditions (m24256-bf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. dc characteristics (m24xxx-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. dc characteristics (m24xxx-r and m24xxx-hr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. dc characteristics (m24256-bf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. ac characteristics (m24 xxx-w, m24xxx-r, m24256-bf see table 8 , table 9 table 10 and table 11 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. 1 mhz ac characteristics (m24xxx-hr, see table 9 and table 11 ). . . . . . . . . . . . . . . . . . 26 table 18. so8w ? 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 28 table 19. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 29 table 20. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30 table 21. wlcsp, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. available m24256-bx products (package, voltage range, temperature grade). . . . . . . . . . 33 table 24. available m24512-x products (package, voltage range, temperature grade) . . . . . . . . . . . 33 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
m24512-x, m24256-bx list of figures 5/37 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. wlcsp connections (top view, marking side, wit h balls on the underside) . . . . . . . . . . . . 7 figure 4. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. m24256-bf, m24xxx-r/w ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . 10 figure 6. m24xxx-hr ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. ac test measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 13. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. so8w ? 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 28 figure 15. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 29 figure 16. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. wlcsp, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
description m24512-x, m24256-bx 6/37 1 description the m24512-w, m24512-r, M24512-HR, m24256-bf, m24256-bw, m24256-br and m24256-bhr devices are i 2 c-compatible electrically erasable programmable memories (eeprom). they are organized as 64 kb 8 bits and 32 kb 8 bits, respectively. i 2 c uses a two-wire serial interface, comprising a bidirectional data line and a clock line. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in ta bl e 3 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. figure 1. logic diagram table 2. signal names signal name function direction e0, e1, e2 chip enable inputs sda serial data i/o scl serial clock input wc write control input v cc supply voltage v ss ground !)e 3$! 6 ## - x - "x 7# 3#, 6 33 % %
m24512-x, m24256-bx description 7/37 figure 2. so and tssop connections 1. see package mechanical data section for package dimensions, and how to identify pin-1. figure 3. wlcsp connections (top view, marking side, with balls on the underside) 1 ai04035e 2 3 4 8 7 6 5 sda v ss scl wc e1 e0 v cc e2 v cc e1 sda scl v ss wc e0 e2 ai14712
signal description m24512-x, m24256-bx 8/37 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 6. indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bidirectional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 6. indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code. when not connected (left floating), these inputs are read as low (0,0,0). figure 4. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. when unconnected, the signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
m24512-x, m24256-bx signal description 9/37 2.5 v ss ground v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 8 and ta b l e 9 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc , the v cc rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise in v cc ), the device does not respond to any instruction until v cc reaches the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 8 and ta bl e 9 ). when v cc passes over the por threshold, the device is reset and enters the standby power mode. however, the device must not be accessed until v cc reaches a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range. in a similar way, during power-down (continuous decrease in v cc ), as soon as v cc drops below the power on reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (where v cc decreases continuously), the device must be in the standby power mode (mode reached after decoding a st op condition, assuming that there is no internal write cycle in progress).
signal description m24512-x, m24256-bx 10/37 figure 5. m24256-bf, m24xxx-r/w ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 6. m24xxx-hr ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz 1 10 100 10 100 1000 bus line capacitor (pf) bus line pull-up resistor (k ) f c = 400 khz, t low = 1.3 s rbus x cbus time constant must be less than 500 ns i2c bus master m24xxx r bus v cc c bus scl sda ai14796 1 10 100 10 100 bus line capacitor (pf) bus line pull-up resistor (k ) f c = 1 mhz, t low = 500 ns, time constant r bus x c bus must be less than 150 ns time constant r bus x c bus must be less than 270 ns ai14795b i2c bus master m24xxx r bus v cc c bus scl sda f c = 1 mhz, extended case where t low = 700 ns,
m24512-x, m24256-bx signal description 11/37 figure 7. i 2 c bus protocol table 3. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1010e2e1e0rw table 4. most significant address byte b15 b14 b13 b12 b11 b10 b9 b8 table 5. least significant address byte b7 b6 b5 b4 b3 b2 b1 b0 scl sda scl sda sda start condition sda input sda change ai00792c stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
device operation m24512-x, m24256-bx 12/37 3 device operation the device supports the i 2 c protocol. this is summarized in figure 7. . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the m24256-bx and m24512-x devices are always slaves in all communications. 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 3.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write command triggers the internal write cycle. 3.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 3.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
m24512-x, m24256-bx device operation 13/37 3.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in table 3. (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. table 6. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x re-start, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 128 for 512 kbit devices start, device select, rw = 0 64 for 256 kbit devices
device operation m24512-x, m24256-bx 14/37 figure 8. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120d page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
m24512-x, m24256-bx device operation 15/37 3.6 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 9. , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a period of time from the start condition until the end of the two address byte s) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 8. . each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte ( table 4. ) is sent first, followed by the least significant byte ( table 5. ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. 3.7 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 9. 3.8 page write the page write mode allows up to 64 bytes (for the m24256-bx) or 128 bytes (for the m24512-x) to be written in a si ngle write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b15-b6 for the m24256-bx, and b15-b7 for the m24512-x) ar e the same. if more bytes are sent than will fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 64 bytes (for the m24256-bx) or from 1 to 128 bytes (for the m24512-x) of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (the 7 least sign ificant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition.
device operation m24512-x, m24256-bx 16/37 3.9 ecc (error correction code) and write cycling the m24256-bx and m24512-x devices offer an ecc (error correction code) logic which compares each 4-byte word with its six asso ciated ecc eeprom bits. as a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ecc detects it and replaces it by the correct value. the read relia bility is therefor e much improved by the use of this feature. note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ecc bits), that is, the addressed byte is cycled together with the other three bytes making up the word. it is therefore recommended to write by word (4 bytes) in order to benefit from the larger amount of write cycles. the m24256-bx and m24 512-x devices are qualified at 1 m illion (1 000 000) write cycles, using a cycling routine that writes to the device by multiples of 4-bytes. figure 9. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106d page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
m24512-x, m24256-bx device operation 17/37 figure 10. write cycle polling flowchart using ack 3.10 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 16. , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 10. , is: initial condition: a writ e cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847d next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
device operation m24512-x, m24256-bx 18/37 3.11 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device?s internal address counter is incremented by one, to point to the next byte address. 3.12 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 11. ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 3.13 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 11. , without acknowledging the byte. 3.14 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 11. the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h.
m24512-x, m24256-bx device operation 19/37 figure 11. read mode sequences 1. the seven most significant bits of the dev ice select code of a random read (in the 1 st and 4 th bytes) must be identical. 3.15 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. start dev sel * byte addr byte addr start dev sel data out 1 ai01105d data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
initial delivery state m24512-x, m24256-bx 20/37 4 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 5 maximum rating stressing the device outside the ratings listed in ta bl e 7 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 7. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for smal l body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on the restriction of the use of certain hazardous substances in electr ical and electronic equip ment (rohs) 2002/95/ec. c v io input or output range ?0.50 v cc + 0.6 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant wi th jedec std jesd22-a114, c1 = 100 pf, r1 = 1500 , r2 = 500 ) ?4000 4000 v
m24512-x, m24256-bx dc and ac parameters 21/37 6 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 12. ac test measurement i/o waveform table 8. operating conditions (m24xxx-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 9. operating conditions (m24xxx-r and m24xxx-hr) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 10. operating conditions (m24256-bf) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c table 11. ac test measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
dc and ac parameters m24512-x, m24256-bx 22/37 table 12. input parameters symbol parameter (1) 1. sampled only, not 100% tested. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l (2) 2. e2,e1,e0: input impedance when the memory is selected (after a start condition). input impedance (e2, e1, e0, wc ) v in < 0.3v cc 30 k z h (2) input impedance (e2, e1, e0, wc ) v in > 0.7v cc 500 k table 13. dc characteristics (m24xxx-w) symbol parameter test conditions (see table 8 and table 11 ) min. max. unit i li input leakage current (scl, sda, e0, e1, e2) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 1ma v cc = 5.5 v, f c = 400 khz (rise/fall time < 50 ns) 2ma i cc0 supply current (write) during t w , 2.5 v < v cc < 5.5 v 5 (1) 1. characterized value, not tested in production. ma i cc1 standby supply current device not selected (2) , v in = v ss or v cc , v cc = 2.5 v 2. the device is not selected after power-up, after a read command (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write command). device grade 3 5 a device grade 6 2 v in = v ss or v cc , v cc = 5.5 v 5 a v il input low voltage (scl, sda, wc ) ?0.45 0.3v cc v v ih input high voltage (scl, sda, wc ) 0.7v cc v cc +0.6 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v 0.4 v
m24512-x, m24256-bx dc and ac parameters 23/37 table 14. dc characteristics (m24xxx-r and m24xxx-hr) symbol parameter test conditions (in addition to those in table 9 ) min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.8 v, f c = 400 khz (rise/fall time < 50 ns) 0.8 ma v cc = 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 1ma v cc = 5.0 v, f c = 400 khz (rise/fall time < 50 ns) 2ma 1.8 v < v cc < 5.5 v, f c = 1 mhz (1) (rise/fall time < 50 ns) 1. only for m24xxx-hr6. 2.5 ma i cc0 supply current (write) during t w , 1.8 v < v cc < 5.5 v 5 (2) 2. characterized value, not tested in production. ma i cc1 standby supply current device not selected (3) , v in = v ss or v cc , v cc = 1.8 v 3. the device is not selected after power-up, after a read command (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write command). 1a device not selected (3) , v in = v ss or v cc , v cc = 2.5 v 2a device not selected (3) , v in = v ss or v cc , v cc = 5.5 v 3a v il input low voltage (scl, sda, wc ) 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc 5.5 v ?0.45 0.3 v cc v ih input high voltage (scl, sda, wc ) 1.8 v v cc < 2.5 v 0.75v cc v cc +1 v 2.5 v v cc 5.5 v 0.7v cc v cc +1 v ol output low voltage i ol = 1 ma, v cc = 1.8 v 0.2 v i ol = 2.1 ma, v cc = 2.5 v 0.4 v i ol = 3.0 ma, v cc = 5.5 v 0.4 v
dc and ac parameters m24512-x, m24256-bx 24/37 table 15. dc characteristics (m24256-bf) (1) 1. preliminary data. symbol parameter test condition (in addition to those in table 9 ) min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.7 v, f c = 400 khz (rise/fall time < 50 ns) 0.8 ma v cc = 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 1ma v cc = 5.0 v, f c = 400 khz (rise/fall time < 50 ns) 2ma 1.7 v < v cc < 5.5 v, f c = 1 mhz (2) (rise/fall time < 50 ns) 2. only for m24xxx-hr6. 2.5 ma i cc0 supply current (write) during t w , 1.7 v < v cc < 5.5 v 5 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 1.7 v 4. the device is not selected after power-up, after a read command (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write command). 1a device not selected (4) , v in = v ss or v cc , v cc = 2.5 v 2a device not selected (4) , v in = v ss or v cc , v cc = 5.5 v 3a v il input low voltage (scl, sda, wc ) 1.7 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc 5.5 v ?0.45 0.3 v cc v ih input high voltage (scl, sda, wc ) 1.7 v v cc < 2.5 v 0.75v cc v cc +1 v 2.5 v v cc 5.5 v 0.7v cc v cc +1 v ol output low voltage i ol = 1 ma, v cc = 1.7 v 0.2 v i ol = 2.1 ma, v cc = 2.5 v 0.4 v i ol = 3.0 ma, v cc = 5.5 v 0.4 v
m24512-x, m24256-bx dc and ac parameters 25/37 table 16. ac characteristics (m24xxx-w, m24xxx-r, m24256-bf see table 8 , table 9 table 10 and table 11 ) symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda (out) fall time 20 100 ns t xh1xh2 (2) 2. values recommended by i2c- bus/fast-mode specification. t r input signal rise time 20 300 ns t xl1xl2 (2) t f input signal fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (3) 3. to avoid spurious start and stop conditions, a minimum delay is pl aced between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (4) 4. for a re-start condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 5 ms t ns pulse width ignored (input filter on scl and sda) - single glitch 100 ns
dc and ac parameters m24512-x, m24256-bx 26/37 table 17. 1 mhz ac characteristics (m24xxx-hr, see table 9 and table 11 ) test conditions specified in table 9 symbol alt. parameter min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 300 - ns t clch t low clock pulse width low 400 - ns t xh1xh2 (1) 1. values recommended by the i2 c-bus fast-mode specification. t r input signal rise time 20 300 ns t xl1xl2 (1) t f input signal fall time 20 300 ns t dl1dl2 (2) 2. characterized only, not tested in production. t f sda (out) fall time 20 100 ns t dxcx t su:dat data in setup time 80 - ns t cldx t hd:dat data in hold time 0 - ns t clqx t dh data out hold time 50 - ns t clqv (3)(4) 3. to avoid spurious start and st op conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. 4. t clqv is the time (from the falling edge of scl) required by the sda bus line to reach 0.8v cc , assuming that the r bus c bus time constant is less than 150 ns (as specified in figure 5 ). t aa clock low to next data va lid (access time) 50 500 ns t chdx (5) 5. for a restart condition, or following a write cycle. t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t w t wr write time - 5 ms t ns (2) pulse width ignored (input filter on scl and sda) -50ns
m24512-x, m24256-bx dc and ac parameters 27/37 figure 13. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795e start condition tchcl txh1xh2 txh1xh2 txl1xl2 txl1xl2 data valid tdl1dl2
package mechanical data m24512-x, m24256-bx 28/37 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 14. so8w ? 8-lead plastic small outline, 208 mils body width, package outline 1. drawing is not to scale. table 18. so8w ? 8-lead plastic small outline, 208 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 2.5 0.0984 a1 0 0.25 0 0.0098 a2 1.51 2 0.0594 0.0787 b 0.4 0.35 0.51 0.0157 0.0138 0.0201 c 0.2 0.1 0.35 0.0079 0.0039 0.0138 cp 0.1 0.0039 d 6.05 0.2382 e 5.02 6.22 0.1976 0.2449 e1 7.62 8.89 0.3 0.35 e 1.27 - - 0.05 - - k 0 10 0 10 l 0.5 0.8 0.0197 0.0315 n (number of pins) 8 8 6l_me e n cp b e a2 d c l a1 k e1 a 1
m24512-x, m24256-bx package mechanical data 29/37 figure 15. so8n ? 8-lead plastic small outlin e, 150 mils body width, package outline 1. drawing is not to scale. table 19. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.75 0.0689 a1 0.1 0.25 0.0039 0.0098 a2 1.25 0.0492 b 0.28 0.48 0.011 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.1 0.0039 d 4.9 4.8 5 0.1929 0.189 0.1969 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h 0.25 0.5 0.0098 0.0197 k 08 08 l 0.4 1.27 0.0157 0.05 l1 1.04 0.0409 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical data m24512-x, m24256-bx 30/37 figure 16. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 20. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
m24512-x, m24256-bx package mechanical data 31/37 figure 17. wlcsp, 0.5 mm pitch, package outline 1. drawing is not to scale. table 21. wlcsp, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 0.60 0.55 0.65 0.0236 0.0217 0.0256 a1 0.245 0.22 0.27 0.0096 0.0087 0.0106 a2 0.355 0.330 0.380 0.0140 0.0130 0.0150 b ? 0.311 ? 0.0122 d 1.97 1.95 1.99 0.0776 0.0768 0.0783 e 1.785 1.765 1.805 0.0703 0.0695 0.0711 e 0.5 0.0197 e1 0.866 0.0341 e2 0.25 0.0098 e3 0.433 0.0170 f 0.552 0.502 0.602 0.0217 0.0198 0.0237 g 0.392 0.342 0.442 0.0154 0.0135 0.0174 n (2) 2. n is the total number of terminals. 8 8 d e e2 g 321 b e a b c d e f e3 e1 orientation reference a1 a a2
part numbering m24512-x, m24256-bx 32/37 8 part numbering table 22. ordering information scheme example: m24512? h w mw 6 t p /ab device type m24 = i 2 c serial access eeprom device function 512? = 512 kbit (64 kb 8) 256?b = 256 kbit (32 kb 8) clock frequency blank: f c max = 400 khz h: f c max = 1 mhz operating voltage w = v cc = 2.5 to 5.5 v r = v cc = 1.8 to 5.5 v f = v cc = 1.7 to 5.5 v package mw = so8 (208 mils width) mn = so8 (150 mils body width) dw = tssop8 cs = wlcsp device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = automotive: device tested with high reliability certified flow (1) over ?40 to 125 c 1. st strongly recommends the use of the automo tive grade devices fo r use in an automotive environment. the high reliability certified flow (h rcf) is described in the quality note qnee9801. please ask your nearest st sales office for a copy. option blank = standard packing t = tape and reel packing plating technology p or g = ecopack? (rohs compliant) process (2) 2. used only for device gr ade 3 and wlcsp packages. /a = f8l in csp package /ab = f8l for device grade 3
m24512-x, m24256-bx part numbering 33/37 for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 23. available m24256-bx products (package, voltage range, temperature grade) package m24256-bw 2.5 v to 5.5 v m24256-br 1.8 v to 5.5 v m24256-bhr 1.8 v to 5.5 v m24256-bf 1.7 v to 5.5 v so8n (mn) range 6, range 3 range 6 range 6 - so8w (mw) range 6 - - - tssop (dw) range 6 range 6 range 6 range 6 wlcsp - range 6 - - table 24. available m24512-x products (package, voltage range, temperature grade) package m24512-w 2.5 v to 5.5 v m24512-r 1.8 v to 5.5 v M24512-HR 1.8 v to 5.5 v so8n (mn) range 6, range 3 range 6 range 6 so8w (mw) range 6 - - tssop (dw) range 6 range 6 -
revision history m24512-x, m24256-bx 34/37 9 revision history table 25. document revision history date revision changes 29-jan-2001 1.1 lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated lga8 and so8(wide) packages added references to psdip8 changed to pdip8, and package mechanical data updated 10-apr-2001 1.2 lga8 package mechanical data and illustration updated so16 package removed 16-jul-2001 1.3 lga8 package given the designator ?la? 02-oct-2001 1.4 lga8 package mechanical data updated 13-dec-2001 1.5 document becomes preliminary data test conditions for ili, ilo, zl and zh made more precise vil and vih values unified. tns value changed 12-jun-2001 1.6 document promoted to full datasheet 22-oct-2003 2.0 table of contents, and pb-free opti ons added. minor wording changes in summary description, power-on re set, memory addressing, write operations, read operations. v il (min) improved to ?0.45v. 02-sep-2004 3.0 lga8 package is not for new design. 5v and -s supply ranges, and device grade 5 removed. abso lute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade information clarified. aec-q100-002 compliance. v il specification unified for sda, scl and wc 22-feb-2005 4.0 initial delivery state is ffh (not necessarily the same as erased). lga package removed, tssop8 and so8n packages added (see package mechanical data section and table 22., ordering information scheme). voltage range r (1.8v to 5.5v) also offered. minor wording changes. z l test conditions modified in table 12., input parameters and note 2. added. i cc and i cc1 values for v cc = 5.5v added to table 13., dc characteristics (m24xxx-w). note added to table 13., dc characteristics (m24xxx-w). power on reset paragraph specified. t w max value modified in table 16., ac characteristics (m24xxx-w, m24xxx-r, m24256-bf see table 8, table 9 table 10 and table 11) and note 4 added. plating technology changed in table 22., ordering information scheme. resistance and capacitan ce renamed in figure 6., m24xxx-hr ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz.
m24512-x, m24256-bx revision history 35/37 05-may-2006 5 power on reset paragraph replaced by section 2.6: supply voltage (v cc ) . figure 4: device select code added. ecc (error correction code) and write cycling added and specified at 1 million cycles. i cc0 added and i cc1 specified over the whole voltage range in ta b l e 1 3 and ta bl e 1 4 . pdip8 package removed. packages are ecopack? compliant. small text changes. 16-oct-2006 6 m24256-bw and m24256-br part numbers added. section 3.9: ecc (error correct ion code) and write cycling updated. i cc and i cc1 modified in table 14: dc characteristics (m24xxx-r and m24xxx-hr) . t w modified in table 16: ac characteristics (m24xxx-w, m24xxx-r, m24256-bf see table 8, table 9 table 10 and table 11) . so8narrow package specifications updated (see ta b l e 1 9 and figure 15 ). blank option removed from below plating technology in table 22: ordering information scheme . 02-jul-2007 7 section 2.6: supply voltage (v cc ) modified. section 3.9: ecc (error correct ion code) and write cycling modified. jedec standard and european direct ive references corrected below table 7: absolute maximum ratings . rise/fall time conditions modified for i cc and v ih max modified in table 13: dc characteristics (m24xxx-w) and table 14: dc characteristics (m24xxx-r and m24xxx-hr) note 1 removed from table 13: dc characteristics (m24xxx-w) . so8w package specifications modified in section 7: package mechanical data . table 23: available m24256-bx products (package, voltage range, temperature grade) and table 24: available m24512-x products (package, voltage range, temperature grade) added. 16-oct-2007 8 section 2.5: v ss ground added. small text changes. v io max changed and note 1 updated to latest standard revision in table 7: absolute maximum ratings . note removed from table 12: input parameters . v ih min and v il max modified in table 14: dc characteristics (m24xxx-r and m24xxx-hr) . removed t ch1ch2 , t cl1cl2 and t dh1dh2 , and added t xl1xl2 , t dl1dl2 and note 2 in table 16: ac characteristics (m24xxx-w, m24xxx-r, m24256- bf see table 8, table 9 table 10 and table 11) . t xh1xh2 , t xl1xl2 and note 2 added to table 17: 1 mhz ac characteristics (m24xxx-hr, see table 9 and table 11) . figure 13: ac waveforms modified. package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see section 7: package mechanical data ). table 25. document revision history (continued) date revision changes
revision history m24512-x, m24256-bx 36/37 14-dec-2007 9 1 mhz frequency introduced (M24512-HR root part number). section 2.6.3: device reset modified. figure 5: m24256-bf, m24xxx-r/w ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz modified, figure 6: m24xxx-hr ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz added. t ns moved from ta b l e 1 2 to ta b l e 1 6 . i lo test conditions modified in ta b l e 1 3 . table 14: dc characteristics (m24xxx-r and m24xxx-hr) and ta b l e 1 7 : 1 mhz ac characteristics (m24xxx-hr, see table 9 and table 11) modified. small text changes. 27-mar-2008 10 small text changes. m24256-bhr root part number added. section 2.6.3: device reset on page 9 updated. figure 6: m24xxx-hr ? maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz on page 10 updated. caution removed in section 3.9: ecc (error correction code) and write cycling . 22-apr-2008 11 m24512-w and m24256-bw offered in the device grade 3 option (automotive tem perature range): ? table 8: operating conditions (m24xxx-w) , ? table 13: dc characteristics (m24xxx-w) , ? /ab process letters added to table 22: ordering information scheme , ? table 23: available m24256-bx products (package, voltage range, temperature grade) and ? table 24: available m24512-x products (package, voltage range, temperature grade) updated accordingly). small text changes. 22-dec-2008 12 wlcsp package added (see figure 3: wlcsp connections (top view, marking side, with balls on the underside) and section 7: package mechanical data ). 21-jan-2009 13 m24256-bf part number added (v cc = 1.7 v to 5.5 v voltage range added, see ta bl e 1 0 , ta b l e 1 5 , ta b l e 1 6 and ta b l e 2 3 ). i cc1 test conditions modified in table 13: dc characteristics (m24xxx-w) , table 14: dc characteristics (m24xxx-r and m24xxx-hr) and table 15: dc characteristics (m24256-bf) . table 25. document revision history (continued) date revision changes
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